| Certificate/Reg.-No. | 968/FSP 1923.00/20 |
| Type of Certificate | A-FS&CS Certificate |
| Certificate Holder | ARM Ltd. |
| Product Category | Software > Others Compliant Items |
| Subject | General purpose microprocessor design including safety features |
| Type Designation | ARM Cortex-R52 Processor IP Core Revision r1p1 and r1p2 |
| Codes and Standards |
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| Scope and Result | The ARM Cortex-R52 Processor IP Core complies with the requirements of IEC 61508 for SIL 3 regarding the avoidance of systematic faults for a Compliant Item and complies with the requirements of ISO 26262 for ASIL D regarding the avoidance of systematic faults for a Safety Element out of Context (SEooC). Based on an exemplary configuration, ARM showed that the target values for the random hardware fault metrics according to ISO 26262-5, Clauses 8 and 9 for ASIL D can be met. As a result this Cortex-R52 Processor can be used in safety-related applications up to SIL 3 according IEC 61508 and up to ASIL D according to ISO 26262. |
| Specific Provisions | The requirements and constraints mentioned in the Cortex-R52 Safety Manual have to be taken into account by the user. |
| Valid Until | 2025-10-26 |
| Appendixes | n/a |
| Download Certificate | 968_FSP_1923_00_20_en_el.pdf |
| Certificate/Reg.-No. | Certificate Holder | Product Category | Product Tested | Type Designation | Details |
|---|
| 968/FSP 1923.00/20 | ARM Ltd. | Software → Others | General purpose microprocessor design including safety features | ARM Cortex-R52 Processor IP Core Revision r1p1 and r1p2 | View Details | View PDF |
| 968/FSP 1923.00/20 | ARM Ltd. | Compliant Items | General purpose microprocessor design including safety features | ARM Cortex-R52 Processor IP Core Revision r1p1 and r1p2 | View Details | View PDF |
Remark: In case of missing entries this is due to restrictions by the certificate holder
